The present invention relates to a switch fabric architecture. More specifically, the present invention provides a shared memory switch architecture which may be employed to switch frames or packets of arbitrary lengths between any of its ports with sustained high speed throughputs.
Shared memory architectures are advantageous for high speed switches with many ports because they make more efficient use of memory. That is, if the memory resides in the ports themselves, the memory in idle ports sits unused while the memory in active ports may be overworked, particularly where the transmission protocol allows very large packets. In addition, where the transmission protocol for which the switch is designed has multicast requirements (e.g., Ethernet), shared memory only requires that that a multicast packet be written to memory once. The multiple ports for which the multicast packet is intended then read the same memory location, an operation which requires no more overhead than if the ports were reading different memory locations. Because of this suitability, shared memory architectures are particularly popular for implementing Ethernet switches.
Conventional approaches to designing such architectures employ synchronous circuits and design flows which face significant obstacles, particularly as both the number of ports and the required speed of each port continue to increase. It is therefore desirable to provide alternatives to such approaches which can keep pace with the increasing demands for performance.